![]() ![]() ISE creates a skeleton test fixture (a.k.a. Click Next, and you'll be prompted to associate the file with a module choose full_adder, click Next, then click Finish. ![]() Select Verilog Test Fixture (not Verilog Module) and give your file a name such as "test_full_adder". Right-click on full_adder.v in the Sources window and choose New Source. Run the Check Syntax process (under Synthesize) to make sure your code is entered correctly, and save your design. You can use your own code, or copy the solution below: This tutorial will use a full adder that is the same as the one you created in Lab 0. If you accidentally select a simulator other than Modelsim for your project, or if you open a previous project that had a different simulator selected, you can change the simulator by right-clicking on xc2vp30-7ff896 in the Sources window in ISE and selecting Properties. ![]()
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